VLSI · Verilog · RTL Design
Hi, I'm Aditya S Malagi
Electronics & Communication Engineering student passionate about VLSI design, FPGA systems, and RTL verification. Building hardware, one register at a time.
About
A learner in love with logic
I'm an Electronics & Communication Engineering student with a strong interest in VLSI design, FPGA systems, and RTL verification. I have hands-on experience with Verilog-based digital design — from FSMs to memory modules — and I'm proficient in C, Python, and Verilog. I'm actively learning SystemVerilog and UVM, and I'm seeking an entry-level role in RTL design or verification.
B.Tech in Electronics and Communication
CMR University, Bangalore · Oct 2024 – Present
CGPA: 8.9
Chancellor's List of Students
CMR University · 2025 · Recognition
Recognized for outstanding academic performance in ECE.
RTL Design & Verification Workshop
The Silicon Sandbox · Oct 2025
5-day hands-on workshop covering Verilog, SystemVerilog, UVM fundamentals, RTL design, simulation, and verification methodologies.
2-Day Workshop VLSI Design Flow
Hands-on Training · 2-Day Workshop
Completed practical training across the full chip-design pipeline: RTL design fundamentals, synthesis and timing analysis, physical design through placement and routing, and final GDSII generation and sign-off for fabrication.
Projects
Things I've built
8×8 RAM in Verilog HDL with synchronous read/write, address decoding, and Read/Write Enable control.
Moore/Mealy FSM in Verilog that detects the '1010' pattern with verified state transitions.
Platform to store and access previous year question papers with 350+ active users.
APB Master controller in Verilog using FSM with IDLE, SETUP, and ACCESS states for data transfer.
Solar-assisted e-bike — motor integration, power systems, and energy efficiency.
Skills
My toolkit
Programming
Software & EDA Tools
Core Knowledge
Embedded Systems
Communication & Debugging
Certifications & Courses
Learning timeline
Oct 2024 · LinkedIn Learning
C Language
Core C fundamentals — data types, control flow, functions, pointers, arrays, structures, and memory management, with a focus on writing efficient embedded-friendly code.
View certificateOct 2024 · LinkedIn Learning
Arduino Uno
Practical introduction to Arduino Uno development, including circuit interfacing, digital and analog I/O, sensor integration, and embedded prototyping.
Jun 2025 · Simplilearn
Python Basics
Python essentials — syntax, data structures, loops, functions, file handling, and object-oriented basics, applied to scripting and automation tasks.
View certificateAug 2025 · Spoken Tutorial, IIT Bombay
C/C++ Language
Strengthened programming fundamentals in C and C++, covering structured and object-oriented programming, functions, arrays, pointers, classes, and problem-solving.
2-Day Workshop
End-to-End VLSI Design Flow
Completed practical training across the full chip-design pipeline: RTL design fundamentals, synthesis and timing analysis, physical design through placement and routing, and final GDSII generation and sign-off for fabrication.
Oct 2025 · The Silicon Sandbox
5-Day Workshop on RTL Design & Verification
Hands-on training in RTL design and verification workflows, including Verilog/SystemVerilog modeling, simulation, testbench development, and digital design debugging.
Oct 2025 · Simplilearn
n8n Course: No-Code AI Agent Builder
Built automated AI-agent workflows with n8n using visual nodes, application integrations, triggers, data routing, and no-code orchestration techniques.
View certificateJan 2026 · Udemy
Verilog for an FPGA Engineer with Xilinx Vivado Design Suite
Applied Verilog HDL to FPGA design using Xilinx Vivado, covering RTL coding, simulation, synthesis, constraints, implementation, and hardware-oriented verification.
View certificateMar 2026 · Udemy
Computer Architecture and Computer Organization Masterclass
Studied processor architecture, instruction execution, memory hierarchy, cache organization, pipelining, I/O systems, and the relationship between hardware and software.
View certificate